1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a circuit configuration of a refreshing control circuit of a DRAM (Dynamic Random Access Memory) with a complete hidden refreshing function.
2. Description of the Background Art
Information stored in a DRAM with a complete hidden refreshing function is held by accumulating charges in a capacitor provided in a memory cell.
To prevent the stored information from being destroyed by a leak current, it is therefore necessary to periodically perform what is called a refreshing operation. The refreshing operation is performed by sequentially selecting word lines provided for rows of memory cells, reading and amplifying micro signals stored in all the memory cells on a selected word line, and executing rewriting. Even if the voltage of a storage node in a memory cell drops due to a leak current or the like, it is reproduced to an initial value.
By continuously sequentially selecting all the word lines, information stored in all the memory cells is reproduced, and storage information of the entire chip is held.
When the maximum refresh interval at which data of all the memory cells can be guaranteed is set as xe2x80x9ctrefmxxe2x80x9d and xe2x80x9cnxe2x80x9d denotes the number of word lines, to refresh the word lines in refresh cycles tcrf at regular intervals so as to prevent stored information from being destroyed by a leak current or the like, tcrfxe2x89xa6trefmx/n has to be set.
FIG. 21 is a block diagram of a row selection control circuit 2000 for performing a conventional refreshing control included in a row decoder.
Row selection control circuit 2000 has a refresh timer 100, a refresh address generating circuit 200, and an internal address generating circuit 300.
Refresh timer 100 is a circuit for generating a refresh clock signal RCLK for specifying a cycle tcrf of executing the refreshing operation.
Refresh address generating circuit 200 is a circuit for receiving refresh clock signal RCLK, generating a refresh address in the refreshing operation, and outputting the refresh address to internal address generating circuit 300. In the refreshing operation, synchronously with refresh clock signal RCLK, counting of a row address for refreshing or the like is performed.
Internal address generating circuit 300 selects either an external address as an input signal or the refresh address and generates an internal address to designate a row address in a memory cell array.
To normally execute the refreshing operation, refresh timer 100 therefore has to oscillate refresh clock signal RCLK at a predetermined frequency (cycle) so as to designate each of word lines to be sequentially refreshed in accurate cycles determined according to the refresh cycle.
In refresh timer 100 in which a ring oscillator or the like is usually used, however, for example, when the power is turned on, it takes some time until the power becomes stable. Consequently, an oscillation period is unstable.
In the conventional refreshing control circuit configuration, therefore, since unstable refresh clock signal RCLK is supplied to refresh address generating circuit 200, there is the possibility of causing an erroneous operation such that a refresh address is not accurately generated.
An object of the invention is to provide a semiconductor device capable of preventing an erroneous operation in a refreshing control in a period where the state of refresh clock signal RCLK is unstable, typically at power-on.
A semiconductor memory device of the invention has: a memory array having a plurality of memory cells arranged in a matrix; a refresh timer for generating a refresh clock having a predetermined refresh cycle; a refresh executing circuit for sequentially refreshing the plurality of memory cells part by part on the basis of the cycle of the refresh clock; and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period in which the cycle of the refresh clock is unstable.
According to the semiconductor memory device, by providing the refresh control circuit between the refresh timer and the refresh executing circuit, the transmission of the refresh clock to the refresh executing circuit can be stopped in the predetermined period in which the cycle of the refresh clock is easy to become unstable. Thus, an erroneous operation of the circuit can be prevented.
Preferably, the refreshing control circuit sets a period which is a predetermined time elapsed since an operation source voltage of the refresh timer is started to be applied as the predetermined period.
Consequently, the transmission of the unstable refresh clock can be stopped in the predetermined time since the operation source voltage of the refresh timer is started to be applied.
Particularly, the refreshing control circuit includes: a first power-on reset circuit for generating a first initialization control signal which is activated when the operation source voltage exceeds a first threshold voltage at power-on; a delay circuit for delaying the first initialization control signal from the power-on reset circuit; and a logic circuit for forcedly fixing a signal level of the refresh clock until the first initialization control signal delayed by the delay circuit is activated.
Since the refresh control circuit includes the power-on reset circuit for receiving the operation source voltage and outputting the initialization control signal, the delay circuit for delaying the initialization control signal, and the logic circuit for forcedly fixing the signal level of the refresh clock until the initialization control signal delayed by the delay circuit is activated, the refresh clock can be stopped until the initialization control signal delayed by the delay circuit is activated.
Particularly, the semiconductor memory device further includes an internal circuit whose circuit state is initialized at the power-on, and initialization of the circuit state in the internal circuit is executed on the basis of the first initialization control signal from the first power-on reset circuit.
The power-on reset circuit can be used as a circuit dedicated to the refresh control circuit or can be commonly used by other internal circuits.
Particularly, the semiconductor memory device further includes: a second power-on reset circuit for generating a second initialization control signal which is activated when the operation source voltage exceeds a second threshold voltage at the power-on; and an internal circuit whose circuit state is initialized in response to the second initialization control signal.
By providing the power-on reset circuit also used by other internal circuits and the power-on reset circuit used for the refresh control circuit separately, the rising of the initialization control signal of each circuit can be independently designed.
Particularly, the delay circuit has: a plurality of signal routes arranged in parallel and having different signal propagation times; and a selection circuit for transmitting the first initialization control signal to one of the plurality of signal routes.
By having the plurality of signal routes of different signal propagation times and the selection circuit for transmitting the signal to one of the plurality of signal routes, the delay circuit can vary the delay time.
Particularly, the selection circuit has a distribution switch selectively formed between a node to which the first initialization control signal is transmitted and the plurality of signal routes.
With the configuration that the selection circuit has the distribution switch selectively formed between the plurality of signal routes having different signal propagation times, the delay time can be changed also in the process of manufacturing a wafer by using a masking process.
Particularly, the selection circuit has a fuse element which can be blown from the outside, the selection circuit generates a selection signal having a signal level according to whether the fuse element is blown or not, and the selection circuit further has a signal transmission gate for selectively transmitting the first initialization control signal to one of the plurality of signal routes in accordance with the selection signal.
Since the selection circuit has the fuse element which can be blown from the outside in a nonvolatile manner, generates a selection signal having a signal level according to whether the fuse element is blown or not, and further has a signal transmission gate for selectively transmitting the initialization control signal to one of the plurality of signal routes in accordance with the selection signal, the delay time can be changed even after the wafer manufacturing process.
Particularly, the selection circuit further has a test circuit for generating the selection signal in accordance with a test signal input from the outside in a test mode irrespective of whether the fuse element is blown or not.
Since the selection circuit further has the fuse element which can be blown from the outside in a nonvolatile manner, generates a selection signal having a signal level according to whether the fuse element is blown or not, has a transmission gate for selectively transmitting the initialization control signal to one of the plurality of signal routes in accordance with the selection signal, and further has the test circuit for generating the selection signal irrespective of whether the fuse element is blown or not, the fuse can be falsely blown, and delay time can be set by signal route selection of higher accuracy.
Particularly, the selection circuit has a pad electrically coupled to one of a plurality of voltages, the selection circuit generates a selection signal having a signal level according to a voltage of the pad, and the selection circuit further has a signal transmission gate for selectively transmitting the first initialization control signal to one of the plurality of signal routes in accordance with the selection signal.
Since the selection circuit has the pad electrically coupled to one of a plurality of voltages, generates a selection signal having a signal level according to one of the plurality of voltages coupled to the pad, and further has the transmission gate for selectively transmitting the initialization control signal to one of the plurality of signal routes in accordance with the selection signal, the delay time can be changed by a signal from the external pad.
Particularly, the selection circuit further has a test circuit for generating the selection signal in accordance with a test signal input from the outside in a test mode irrespective of the voltage of pad.
Since the selection circuit has the pad electrically coupled to one of a plurality of voltages, generates a selection signal having a signal level according to one of the plurality of voltages coupled to the pad, has the transmission gate for selectively transmitting the initialization control signal to one of the plurality of signal routes in accordance with the selection signal, and further has the test circuit for generating the selection signal irrespective of whether or not the pad is electrically coupled to one of the plurality of voltages, the pad can be falsely coupled to a voltage. Thus, the delay time can be set by signal route selection of higher accuracy.
Particularly, the selection circuit has a rewritable memory circuit for holding data, the selection circuit generates a selection signal having a signal level according to the data read from the memory circuit, and the selection circuit further has a signal transmission gate for selectively transmitting the first initialization control signal to one of the plurality of signal routes in accordance with the selection signal.
Since the selection circuit has the rewritable memory circuit for holding data, generates a selection signal having a signal level according to the data by reading the data held in the memory circuit, and further has a signal transmission gate for selectively transmitting the initialization control signal to one of the plurality of signal routes in accordance with the selection signal, the delay time can be changed by rewriting the memory.
Particularly, the semiconductor memory device is mounted on one of a plurality of chips sealed in the same package, the selection circuit generates a selection signal having a signal level according to the data input from a data-rewritable memory circuit formed in another one of the plurality of chips, and the selection circuit further has a signal transmission gate for transmitting the first initialization control signal to one of the plurality of signal routes in accordance with the selection signal.
Since the semiconductor memory device of the invention is mounted on one of a plurality of chips sealed in the same package, and the selection circuit generates a selection signal having a signal level according to data input from a data-rewritable memory circuit formed on another one of the plurality of chips, and further has a signal transmission gate for transmitting the initialization control signal to one of the plurality of signal routes having different signal propagation times in accordance with the selection signal, the delay time can be changed by rewriting the memory circuit formed on the another one of the plurality of chips.
Preferably, the refreshing control circuit sets, as the predetermined period, a period of a predetermined time elapsed since a timing at which a predetermined control signal input from the outside is set in a predetermined state.
The refreshing control circuit can stop transmission of an unstable refresh clock during the period of a predetermined time elapsed since a timing at which a predetermined control signal input from the outside is set in a predetermined state.
The refreshing control circuit includes: a signal generating circuit for generating a refresh status control signal which is activated when the predetermined control signal enters the predetermined status; a delay circuit for delaying the refresh status control signal from the signal generating circuit; and a logic circuit for forcedly fixing a signal level of the refresh clock until the refresh status control signal delayed by the delay circuit is activated.
By including the timing control circuit for generating a timing signal which is activated when the predetermined control signal enters the predetermined status; the delay circuit for delaying the timing signal from the timing control circuit; and the logic circuit for forcedly fixing a signal level of the refresh clock until the timing signal delayed by the delay circuit is activated, transmission of the unstable refresh clock can be stopped.
Particularly, the predetermined control signal is a single signal, and the predetermined control signal is not used in a normal operation of the semiconductor memory device.
By using the single signal which is not used in a normal operation of the semiconductor memory device as the predetermined control signal, the configuration of the refresh control circuit is simplified.
Particularly, the refreshing control circuit starts the predetermined period when the predetermined control signal maintains the predetermined status for a predetermined time.
When the predetermined control signal maintains the predetermined status for a predetermined time, the refresh control circuit can stop the transmission of an unstable refresh clock.
Particularly, the predetermined control signal includes a plurality of signals used in a normal operation of the semiconductor memory device, and the predetermined status corresponds to a predetermined combination of signal levels of the plurality of signals.
With the configuration that the predetermined control signal includes a plurality of signals used in a normal operation of the semiconductor memory device, and the predetermined status corresponds to a predetermined combination of signal levels of the plurality of signals, the noise-immune refresh control circuit capable of preventing erroneous operation can be designed.
Particularly, the refreshing control circuit starts the predetermined period when the predetermined control signal maintains the predetermined status for a predetermined time.
When the predetermined control signal maintains the predetermined status for a predetermined time, the refresh control circuit can stop the transmission of an unstable refresh clock.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.